1. Field of Invention
The present invention relates to self-timing read architecture for a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory is composed of data storage cells arranged in rows and columns. The process of reading from the memory is accomplished by means of control, address and input/output signals. At the time of reading, a set of external control signals and a clock are activated. The memory cell from which the data is to be read is accessed and then the data is read by the read circuitry connected between the output data lines of the memory.
The read circuitry performs the reading operation by sensing the voltage difference developed across the data lines. However, in order to ensure that desired data is read correctly, the read operation should be performed only when a sufficient voltage differential has been developed across the data lines. This is done by ensuring a predetermined time delay between accessing the memory cell and reading the bit value. This time delay is controlled by a timing circuit coupled to the read circuitry. The time delay can be determined by the memory structure and its likely behavior, i.e., likely time for a sufficient voltage difference to be developed, is known. However, the memory behavior depends on other factors such as memory size and PVT (process voltage and temperature conditions). Moreover, since different process tolerances are involved in the manufacture of memories, this means that any two memories may not have identical behavior.
To overcome the above-mentioned problems, “dummy cells” have been successfully used in semiconductor memory devices. These cells are provided in the memory region of the semiconductor device and have the same structure as the actual memory cells. As a result, it takes the same time for a predetermined voltage differential to be developed across a dummy bit line as in the case of normal bit line. This fact can be exploited to make the timing circuit responsive to the operating conditions of the memory. The timing circuit receives the voltage developed on the dummy bit line as a control input. It produces a timing signal when the voltage developed on dummy bit line reaches a predetermined value. The timing signal, also known as ‘sense-on’ signal, then simulates the read circuitry to read the voltage across the normal bit line.
In one of the configurations commonly used, the dummy memory cell is provided farther away than the memory cell, which is farthest away from the control circuit. As a result, the path along which the dummy memory cell signal is retrieved has a timing delay that is longer than that of the critical path that has the longest timing delay in the memory cell array. This ensures that the process of reading the data from all memory cells is properly performed. However, in this configuration the load of driving the dummy bit line is greater than the maximum load that can be incurred when reading data from a normal memory cell. This leads to a problem of higher power consumption.
To overcome this problem, another configuration was introduced in which the dummy memory cell and its associated circuitry are situated at a corner of the memory cell array closest to the control circuit. As a result, the dummy path for emulating a data access path can be implemented as a relatively shorter path, which results in dummy drive circuit having a smaller drive capacity than the signal drive circuit.
However, in all the above mentioned configurations, since the discharge circuit for a normal bit line depends on the position of the normal memory cell that is accessed and the discharge circuit for the dummy bit line is fixed, the dummy bit line and the normal bit line have different resistances. Also, the vertical process gradient causes mismatch between the dummy discharge cell and the normal discharge cell. Since the position of the normal memory cell accessed in every read operation is different, this leads to statistical deviation between predetermined voltage creation on the bit line and the ‘sense-on’ signal arrival. This in turn reduces the speed of the operation of the memory device.
Therefore, there is a need for a semiconductor memory device that is provided with a self-timing circuit so as to ensure stability against variation in operating conditions where the self-timing circuit ensures high speed and robustness.